This invention relates generally to improvements in pipelined computer processors that execute relatively simple instructions in hardware controlled execution units and execute relatively complex instructions in a milli-mode architected state with vertical microcode (i.e. millicode) routines executing in the same hardware controlled execution units. More particularly, this invention relates to a specialized millicode instruction which reduces the number of branch instructions required to test combinations of millicode branch points.
A new generation of S/390 ESA CMOS machines were introduced in 1997 by International Business Machines Corporation known as the G4 generation. Included was a pipelined computer processor which provides for the use of millicode. A milli-mode operation enables implementation of complex functions in a large, hardware controlled, pipelined, general purpose digital computer without a microprocessor. Milli-mode implements these complex functions with the flexibility provided by firmware and avoids a packaging problem introduced by the inclusion of microprocessor hardware. Rather than a microprocessor, milli-mode uses the pre-existing dataflow and hardware controlled execution units of a pipe-lined processor to accomplish complex functions. Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These private milli-mode instructions augment the architected instruction set. Milli-mode routines can intermingle the milli-mode only instructions with architected instructions to implement complex functions as illustrated by U.S. Pat. No. 5,694,587, issued Dec. 2, 1997. U.S. Pat. No. 5,694,587 describes specialized millicoded instructions for a PSW Validity Test, Load With Access Test, and Character Translation Assist, which were employed in the IBM machine known as the G4 S/390 machine introduced in 1997. Related to U.S. Pat. No. 5,694,587 were additional applications related to millicode which are implemented in the same G4 S/390 machine introduced in 1997 by International Business Machines Corporation.
However, there are still improvements which may be made in the millicode environment. For example, while executing a millicode routine, it is important to have that routine executed as quickly as possible to improve the overall performance of the system. One of the operations that is done most frequently within a millicode routine is branching. Whenever branches are encountered within a millicode routine, the Instruction Processing Unit of the processor sometimes fetches and decodes instructions located on the incorrect path of the branch. For millicode execution there are many hardware conditions that the millicode can interrogate, which assist in controlling the actual execution of a specific millicode routine. Each of these conditions can be interrogated with a millicode instruction, (e.g. Branch Relative Special (BRS)) but, as before, the hardware may initially predict the wrong path of the branch and start fetching and decoding instructions that will not be executed. In addition, due to the format of the instruction, the branch target can only be 64K bytes away from the BRS, which may not give as much branch capability as the millicode routine would desire. It would be advantageous, therefore, to provide a solution that would reduce the number of branch instructions required to test combinations of millicode branch points, thereby resulting in fewer branches being decoded by the Instruction Processing Unit, and ultimately, fewer fetches down wrong branch paths.
An exemplary embodiment of the present invention is a method and system for reducing the number of branch instructions required to test combinations of millicode branch points. The method is implemented via a pipe-lined computer processor executing a millicode routine. The processor activates a millicode condition code; interrogates a first field of the Test Millicode Branch Points (TMBP) instruction, the results of which determine a logical function to be performed on the millicode condition code; interrogates a second field of the TMBP instruction which specifies a first millicode branch point; interrogates a third field of the TMBP instruction, which specifies a second millicode branch point; and modifies the milli-code condition code based on the results of the interrogating. A conditional branch instruction can then be executed based on the resultant milli-code condition code of the TMBP instruction.